Hisashi Saito, Yasuyuki Miyamoto, and Kazuhito Furuya, "Improvement in Gate Insulation in InP Hot Electron Transistors for High Transconductance and High Voltage Gain", Applied Physics Express, 2, 034501 (2009)

So Nishimura, Kazuhito Furuya, Yasuyuki Miyamoto “Design and Simulation of Hot-Electron Diffraction Oservation by Scanning Probe – Quantitative Evaluation of Observation Possibility –”Jap. J. Appl. Phys. Vol. 47, No. 11, Nov., 2008, pp. 8652-8658.

Chien-I KUO, Heng-Tung HSU , Edward Yi CHANG, Yasuyuki MIYAMOTO , and Wen-Chung TSERN,“InAs High Electron Mobility Transistors with Buried Gate for Ultralow-Power-Consumption Low-Noise Amplifier Application” Jap. J. Appl. Phys. Vol. 47, No. 9, Sept., 2008, pp. 7119–7121

Yasuyuki Miyamoto, Takashi Hasegawa, Hisashi Saito, and Kazuhito Furuya, "RF Characteristics of Schottky-Gate-Controlled Hot Electron Transistor", IEEE Nanotechnology Materials and Devices Conference 2008, We P17, Kyoto, Oct., 2008.

T. Kanazawa, H. Saito, K. Wakabayashi, Y. Miyamoto and K. Furuya, "Lateral Buried Growth of N+-InGaAs Source/Drain Region to Undercut InGaAs Channel Structure for High Drive Current N-type MOSFET" 2008 International Conference on Solid State Devices and Materials (SSDM 2008), G-2-5, Tsukuba, Sept., 2008.

C. Y. Chang, H. T. Hsu, E. Y. Chang, C. I. Kuo and Y. Miyamoto, "InAs-Channel HEMTs for Ultra-Low-Power LNA Applications", 2008 International Conference on Solid State Devices and Materials (SSDM 2008), G-2-3, Tsukuba, Sept., 2008.

Hisashi Saito, Takahiro Hino, Yasuyuki Miyamoto, Kazuhito Furuya, "Hot electron transistor controlled by insulated gate with 70nm-wide emitter", EEE 20th Conference on Indium Phosphide and Related Materials (IPRM’08), WeP72, Versailles - France, May, 2008

Chien-I Kuo, Edward Yi Chang, Chia-Yuan Chang, Heng-Tung Hsu, Yasuyuki Miyamoto, "Investigation of impact ionization from InXGa1-XAs to InAs channel HEMTs for high speed and low power applications", IEEE 20th Conference on Indium Phosphide and Related Materials (IPRM’08), WeP68, Versailles - France, May, 2008

Chien-I Kuo, Heng-Tung Hsu, Edward Yi Chang, Chia-Yuan Chang, Yasuyuki Miyamoto, Suman Datta, Marko Radosavljevic, Guo-Wei Huang, and Ching Ting Lee “RF and Logic Performance Improvement of In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel HEMTs Using Gate-Sinking Technology” IEEE Electron Device Lett., vol.29, No. 4, Apr., 2008.

Chien-I Kuo, Heng-Tung Hsu, Edward Yi Chang, Chia-Yuan Chang, Yasuyuki Miyamoto, Suman Datta, Marko Radosavljevic, Guo-Wei Huang, and Ching Ting Lee “RF and Logic Performance Improvement of In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel HEMTs Using Gate-Sinking Technology” IEEE Electron Device Lett., vol.29, No. 4, Apr., 2008.

Chia-Yuan Chang, Heng-Tung Hsu, E. Y. Chang, Chien-I Kuo, S. Datta, M. Radosavljevic, Y. Miyamoto, and Guo-Wei Huang “Investigation of Impact Ionization in InAs-Channel HEMT for High-Speed and Low-Power Applications”, IEEE Electron Dev. Lett., vol.28, no.10, pp.856-858, 2007.

S. Takahashi、T. Miura, H. Yamashita,Y. Miyamoto and K. Furuya,“DC　Characterristics of Heterojunction Bipolar Tranistor　with　Buried SiO2 Wire in Collector,Int Symp.Compound Semiconductors, TuD-P2,Kyoto,Oct,2007

H.Yamashita， T.Miura， S.Takahashi， Y.Miyamoto and K.Furuya　"Fabrication of 200-nm-thick SiO2 wires buried in InP for reduction in collector capacitance in InP/InGaAs DHBT" Topical Workshop on Heterostructure Materials (TWHM2007)， FrC-3 ， Kisarazu/Japan， Aug. 2007.

K. Nishihori and Y. Miyamoto, “Numerical Analysis of the Effect of P-Regions on the I-V Kink in GaAs MESFETs”, Trans. IECE of Japan, vol.E90-C, no.8, pp.1643-1649, (2007).

M. Igarashi, N. Machida, Y. Miyamoto, and K. Furuya, “Cutoff Frequency Characteristics of Insulated-gate Hot-electron Transistors”, 15th International Conference on Nonequilibrium Carrier Dynamics in Semiconductors, (HCIS-15), MoP-45, Tokyo, July, 2007.

A. Suwa, T. Hasegawa, T. Hino, H. Saito, M. Oono, Y. Miyamoto, and K. Furuya, "InP/InGaAs hot electron transistors with insulated gate", Jpn. J. Appl. Phys., vol.46, no.25, pp. L617-L619, (2007)

Chia-Yuan Chang, Edward Yi Chang, Yi-Chung Lien, Yasuyuki Miyamoto, Chien-I Kuo, Sze-Hung Chang and Li-Hsin Chu, "High-PerformanceIn0.52Al0.48As/In0.6Ga0.4As Power Metamorphic High Electron Mobility Transistor for Ka-Band Applications", Jpn. J. Appl. Phys., vol.46, no.6A, pp. 3385-3387, (2007)

T. Hino, A. Suwa, T. Hasegawa, H. Saito, M. Oono, Y. Miyamoto, K. Furuya, "Fabrication of hot electron transistors controlled by insulated gate", 19th International Conference on Indium Phosphide and Related Materials (IPRM'07), PA-11 Matsue, May. 2007

N. Kashio, K. Kurishima, Y. Fukai, S. Yamahata, and Y. Miyamoto, ﾒEmitter layer design for highly reliable and high-speed InP HBTsﾓ, 19th International Conference on Indium Phosphide and Related Materials (IPRM'07) PD1, Matsue, May, 2007.

A. Suwa, I. Kashima, Y. Miyamoto, and K. Furuya, “Increase of collector current in hot electron transistors controlled by gate bias”, Jpn. J. Appl. Phys., vol.46, no.9, pp.L202-204, (2007) [ABSTRACT & PDF ]

Y. Miyamoto, M. Ishida, T. Yamamoto, T. Miura, and K. Furuya, ﾒInP buried growth of SiO2 wires toward reduction of collector capacitance in HBTﾓ, J. Cryst, Growth, 298, 867-870 (2007).

Chia-Yuan Chang, Edward Yi Chang, Yi-Chung Lien, Yasuyuki Miyamoto, Szu-Hung Chen, and Li-Hsin Chu, "High-Performance In0.52Al0.48As/In0.6Ga0.4As Power Metamorphic HEMT for Ka-Band Applications", 2006 IEEE International Conference on Semiconductor Electronics (ICSE2006), Kuala Lumpur, Malaysia, Nov., 2006.

T. Kai, Y. Fukuyama, Y. Miyamoto, K. Furuya, K. Kurishima and S. Yamahata, "Electron Beam Lithography for Non Self-Aligned HBTs with Extremely Narrow Emitter Mesa", 2006 International Microprocesses and Nanotechnology Conference, kanagawa, Kamakura, Oct 2006.

Y. Miyamoto, R. Nakagawa, I. Kashima, A. Suwa, N. Machida, and K. Furuya, "25-nm-wide emitter for InP hot electron transistors without base layer (Invited)", International Topical Workshop "Tera- and Nano-Devices:Physics and Modeling" III.2, Aizu-Wakamatsu, Oct., 2006.

K Furuya, N Machida, M Igarashi, R Nakagawa, I Kashima, M Ishida and Y Miyamoto, "MC simulation of ultrafast transistor using ballistic electron in intrinsic semiconductor and its fabrication feasibility", J. Physics: Conference Series, 38, 208-211,(2006)

Nobuya Machida,Yasuyuki Miyamoto,Kazuhito Furuya, "Charging Time of Double-Layer Emitter in Heterojunction Bipolar Transistor Based on Transmission Formalism", Jpn. J. Appl. Phys. Vol.45 (2006) No.35 pp.L935 - L937 [ABSTRACT & PDF ]

Yasuyuki MIYAMOTO Ryo NAKAGAWA Issei KASHIMA Masashi ISHIDA Nobuya MACHIDA Kazuhito FURUYA "Current Gain and Voltage Gain in Hot Electron Transistors without Base Layer", Trans. IECE of Japan, vol.E89-C, No.7, .pp.972-978, JULY. 2006

Y. Miyamoto, I. Kashima, A. Suwa, and K. Furuya, "Increase in current density at 25-nm-wide emitter for InP hot-electron transistors without base layer", Device Research Conf. V.A-7, University Park, PA, June, 2006.

Y. Miyamoto, M.Ishida, T.Yamamoto, T.Miura, and K.Furuya, " InP Buried growth of SiO2 wires toward reduction of collector capacitance in HBT", International Conference on Metalotganic Vapor Phase Epitaxy, (ICMOVPE), Miyazaki, Japan, May, 2005.

N. Machida, Y. Miyamoto and K. Furuya, "Minimum Emitter Charging Time for Heterojunction Bipolar Transistors,", International Conference on Indium Phosphide and Related ,WP16 , Pronceton, NJ, May 2005.

K. Furuya, N. Machida, R. Nakagawa, I. Kashima, M. Ishida, and Y. Miyamoto, ﾒMC simulation and fabrication of ultrafast transistor using ballistic electron in intrinsic semiconductorﾓ, Second Joint International Conference on New Phenomena in Mesoscopic Systems and Surfaces and Interfaces of Mesoscopic Devices, P28, Maui, USA, Nov. 2005.

Y. Miyamoto, R. Nakagawa, I. Kashima, M. Ishida and K. Furuya, "Low leakage gate current of InP transistors with hot electron extracted by attractive potential around i-InP/metal gate", 2005 International Conference on Solid State Devices and Materials (SSDM 2005), I-2-6, Kobe, September, 2005 Kobe,

Y Miyamoto, R. Nakagawa, I. Kashima, K. Takeuchi, Y. Yamada, T. Fujisaki, M. Ishida, and K. Furuya, "25 nm Wide Emitter and Precise Alignment between Gate and Emitter in InP Hot Electron Transistors", The 6th Topical Workshop on Heterostructure Microelectronics (TWHM 2005), TuC-3, Awaji-shima. August, 2005.

Y. Miyamoto, M. Ishida, T. Nonaka, T. Yamamoto, and K. Furuya,
"Tungsten Buried Growth by Using Thin Flow-Liner for Small Collector Capacitance in InP HBT",
International Conference on Indium Phosphide and Related ,TuA-1-4 , Glasgow, May 2005.

Y. Miyamoto, Y. Watanabe, W. Qiu, and K. Furaya,
"Analysis of lateral current spreading in collector of submicron HBT ",
International Conference on Indium Phosphide and Related ,WP-15 , Glasgow, May 2005.

Kazuhito Furuya, Yasunori Ninomiya, Nobuya Machida and Yasuyuki Miyamoto,
"Double-Slit Interference Observation of Hot Electrons in Semiconductors -- Analysis of Experimental Data --"
Jpn. J. Appl. Phys. Vol. 44 Part 1, no.5A, 2936-2944 (2005) [ABSTRACT & PDF ]

Y. Miyamoto, Y. Shirai, M. Yoshizawa and K. Furuya,
"20 nm Periodical Pattern by Calixarene Resists: Comparison of CMC[4]AOMe with MC[6]AOAc",
2004 International Microprocesses and Nanotechnology Conference, 28P-6-54, Osaka, Oct., 2004

K. Goto,T. Kirigaya,Y. Masuda,Y.-J. Kim,Y. Miyamoto,S. Arai ,
"Design and Experiments of a Near-Field Optical Disk Head for Very High Efficiency",
The Journal of Scanning Microscopies, vol.26, no.5, I-68-I-72, (2004)

Masaki Yoshizawa, Yasuyuki Miyamoto, Hiroyuki Nakano, Tetsuya Kitagawa, and Shigeru Moriya,
"Challenges to ultra-thin resist process for LEEPL",
J. Photopolymer Sci. Technol. 17, 581 (2004).

Masaki Yoshizawa, Shigeru Moriya, Hiroyuki Nakano, Yuichi Shirai, Tatsuo Morita, Tetsuya Kitagawa and Yasuyuki Miyamoto,
" Impact of Latent Image Quality on Line Edge Roughness in Electron Beam Lithography",
Jpn. J. Appl. Phys. Vol. 43 Part 1, no.6B, 3739-3743 (2004) [ABSTRACT & PDF ]

R.Nakagawa, K.Takeuchi, Y.Yamada, Y.Miyamoto and K.Furuya,
"InP Hot Electron Transistors with Reduced Emitter Width for Controllability of Collector Current by Gate Bias",
International Conference on Indium Phosphide and Related Materials,P1-14, Kagoshuma, June 2004.

Kazuki Sasao, Yasuo Azuma, Naotaka Kaneda, Eiji Hase, Yasuyuki Miyamoto and Yutaka Majima,
"Observation of Current Modulation through Self-Assembled Monolayer Molecule in Transistor Structure",
Jpn. J. Appl. Phys. Vol. 43 Part 2, no.3A, L337-L339 (2004) [ABSTRACT & PDF ]

Katsuhiko Takeuchi, Hiroshi Maeda, Ryo Nakagawa, Yasuyuki Miyamoto and Kazuhito Furuya,
"InP Hot Electron Transistors with Emitter Mesa Fabricated between Gate Electrodes for Reduction in Emitter-Gate Gate-Leakage Current",
Jpn. J. Appl. Phys. Vol. 43 Part 2, no.2A, L183-L186 (2004) [ABSTRACT & PDF ]

Keigo Yokoyama, Koji Matuda, Toshihiro Nonaka, Yasuyuki Miyamoto, and Kazuhito Furuya,
"Fabrication of GaInAs/InP heterojunction bipolar transistors with a single tungsten wire as collector electrode",
Jpn. J. Appl. Phys. Vol. 42 part 2, no.12B, pp. L1501-L1503 (2003) [ABSTRACT & PDF ]

Yasuyuki Miyamoto, Ren Yamamoto, Hiroshi Maeda, Katsuhiko Takeuchi, Nobuya Machida, Lars-Erik Wernersson and Kazuhito Furuya,
"InP Hot Electron Transistors with a Buried Metal Gate",
Jpn. J. Appl. Phys.,　vol. 42 part 1, no.12, pp.7221-7226 (2003) [ABSTRACT & PDF ]

K. Furuya , Y. Ninomiya , and Y. Miyamoto,
"Young's Double-Slit Interference Experiment of Hot Electron　in Semiconductors",
Sixth　International　Conference on New Phenomena in Mesoscopic Systems & Fourth International Conference on Surfaces and Interfaces of Mesoscopic Devices, 1.6,Maui, Dec., 2003

Kazuhito Furuya, Yasunori Ninomiya, Nobuya Machida, and Yasuyuki Miyamoto,
"Young’s Double-Slit Interference Observation of Hot Electrons in Semiconductors"
Phys. Rev. Lett. 91, 216803, Nov., (2003) [ABSTRACT & PDF ]

M. Yoshizawa, S. Moriya, H. Nakano, T. Morita,T. Kitagawa and Y. Miyamoto,
"The Impact of Latent Image Quality on Line Edge Roughness in Electron Beam Lithography",
2003 International Microprocesses and Nanotechnology Conference, 30p-6-15

K. Sasao, Y. Azuma, N. Kaneda, E. Hase, Y. Miyamoto and Y. Majima
"Observation of current modulation in SAM-FET fabricated by an air-bridge structure"
The 2003 International Conference on Solid State Devices and Materials, P7-5, Tokyo, Sept., 2003

K. Takeuchi, H. Maeda, R. Makagawa, Y. Miyamoto, and K. Furuya
"InP hot electron transistors using modulation of gate electrodes"
The 2003 International Conference on Solid State Devices and Materials, E-7-3, Tokyo, Sept., 2003

Tsuyoshi Tanaka, Kohichi Tokudome and Yasuyuki Miyamoto ,
"Effects of Low-Oxygen-Content Metalorganic Precursors on AlInAs and High Electron Mobility Transistor Structures with the Thick AlInAs Buffer Layer"
Jpn. J. Appl. Phys. Vol. 42 Part 2, No. 8B, L993-L995 : (2003) [ABSTRACT & PDF ]

K. Furuya , Y. Ninomiya , and Y. Miyamoto
"Young's Double-Slit Interference Experiment of Hot Electron　in Semiconductors"
The 13th International Conference on Nonequilibrium Carrier Dynamics in Semiconductors, Th11.17, July,Modena, 2003

Y. Miyamoto and Y. Tohmori
"Activities of Indium Phosphide in Japan"
(Invited) GaAs Mantech, 11-1, Scottdale, USA, May 2003

T. Tanaka, K. Tokudome, and Y. Miyanmoto,
"Growth of AlInAs using low-oxygen-content metalorganic precursors and application to HEMT strutures",
International Conference on Indium Phosphide and Related Materials,ThB 2.4, Santa Barbara, USA, May 2003.