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研究成果

2017年度

  • T. Kanazawa and Y. Miyamoto, “Development of Field-Effect Transistor Using 2D Layered Hafnium Disulfide (Invited)”, The XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017), 2D06, New Delhi, Inida, Dec. 13, 2017.

  • K. Makiyama, T. Ohki, S. Ozaki, Y. Niida, N. Okamoto, Y. Minoura, M. Sato, Y. Kamada, T. Ishiguro,K. Joshin, N. Nakamura,and Y. Miyamoto,“InAlGaN/GaN-HEMT Device Technologies for High-Power-Density W-band Amplifiers (Invited)” International Conference on Materials and Systems for Sustainability 2017 (ICMaSS2017 ), 30-Nitride-3, Nagoya, Japan, Sept.30, 2017.

  • S. Netsu, T. Kanazawa,V. Upadhyaya,T.Uwanno,T. Amemiya, K. Nagashio,and Y. Miyamoto, "Type II HfS2/MoS2 heterojunction Tunnel FET" 12th Topical Workshop on Heterostructure Microelectronics, (TWHM 2017), 6-3, Kirishima, Kagoshima, Aug 29, 2017

  • D. Nakajun, R. F. T. Fathulah, H. Fujita, E. Yagyu, and Y. Miyamoto, "Multi-level inverter by GaN HEMT on semi-insulating substrate",12th Topical Workshop on Heterostructure Microelectronics, (TWHM 2017),, 4-4, Kirishima, Kagoshima, Aug 29, 2017

  • Y. Miyamoto, D. Nakajun, R. F. T. Fathulah, H. Fujita, and E. Yagyu, “High speed GaN HEMT for power electronics (Invited)”, 12th International Conference on Nitride Semiconductors (ICNS 12), Strasbourg, France, C5.1 July 26, Strasbourg, France, 2017.

  • K. Makiyama, S. Ozaki, Y. Niida, T. Ohki, N. Okamoto, Y. Minoura, M. Sato, Yoichi Kamada, K. Joshin, N. Nakamura, and Y. Miyamoto, “Advanced HEMTs and MMICs Technologies for Next Generation Millimeter-wave Amplifiers(Invited)”, 12th International Conference on Nitride Semiconductors (ICNS 12), C.1.2 July 24, Strasbourg, France, 2017.

  • T.Kanazawa, T. Amemiya, V. Upadhyaya, A. Ishikawa,K. Tsuruta, T. Tanaka, and Y. Miyamoto, "Performance Improvement of HfS2 Transistors by Atomic Layer Deposition of HfO2", IEEE Trans. Nanotechnology, vol.16, no.4, pp.582-587 (2017). DOI: 10.1109/TNANO.2017.2661403

  • N. Kise, S. Iwata, R. Aonuma, K. Ohsawa and Y. Miyamoto,"GaAsSb/InGaAs Double-Gate Vertical Tunnel FET with a Subthreshold Swing of 68mV/dec at Room Temperature", Compound Semiconductor Week 2017, C804, Berlin, Germany, May 2017.

  • K. Makiyama, Y. Niida, S. Ozaki, T. Ohki, N. Okamoto, Y. Minoura, M. Sato, Y. Kamada, K. Joshin, K. Watanabe, Y. Miyamoto,"GaN HEMT Device Technology for W-band Power Amplifiers (Invited)", Compound Semiconductor Week 2017, A6-1, Berlin, Germany, May 2017.

  • V. Upadhyaya, T. Kanazawa, and Y. Miyamoto, "Vacuum Annealing and Passivation of HfS2 FET for Mitigation of Atmospheric Degradation", Trans IEICE vol.E100-C,No.5, pp.453-457, May. 2017.

  • K. Ohsawa, S. Netsu, N. Kise, S. Noguchi, and Y. Miyamoto “Dependence of electron mobility on gate voltage sweeping width and deposition temperature in MOSFETs with HfO2/Al2O3/InGaAs gate stacks” Jpn. J. Appl. Phys., vol.56, no. 4S, 04CG05 2017  DOI: 10.7567/JJAP.56.04CG05

2016年度

  • K. Makiyama, Y. Niida, S. Ozaki, T. Ohki, N. Okamoto, Y. Minoura, M. Sato, Y. Kamada, K. Joshin, K. Watanabe and Y. Miyamoto, "High-Power-Density InAlGaN/GaN-HEMT Technology for W-Band Amplifier (Invited)", 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Austin, TX, Oct. 2016 http://dx.doi.org/10.1109/

  • N. Kise,H. Kinoshita, A. Yukimachi, T. Kanazawa and Y. Miyamoto, "Fin width dependence on gate controllability of InGaAs channel FinFETs with regrown source/drain", Solid-State Electronics, vol.126, pp.92-95, http://dx.doi.org/10.1016/j.sse.2016.09.009

  • A. Yukimachi and Y. Miyamoto, “InGaAs/AlAs triple-barrier p-i-n junction diode for realizing superlattice-based FET for steep slope”, Jpn. J. Appl. Phys., vol.55, 118004 http://dx.doi.org/10.7567/JJAP.55.118004

  • Y. Miyamoto, "Recent progress in compound semiconductor electron devices (Review paper)", IEICE Electronics Express, Vol. 13 (2016) No. 18 pp.1-13, http://doi.org/10.1587/elex.13.20162002

  • K. Ohsawa, N. Kise and Y. Miyamoto, "Deposition Temperature and Al2O3 Thickness Dependence on the Mobility of HfO2/Al2O3/InGaAs Gate Stacks",2016 International Conference on Solid State Devices and Materials (SSDM), PS-6-02, Tsukuba, Japan, Sept. 2016.

  • K. Makiyama, S. Ozaki, T. Ohki, N. Okamoto, Y. Minoura, Y. Niida, Y. Kamada, M. Sato, K. Joshin, K. Watanabe,and Y. Miyamoto, "High-Performance GaN-HEMT Technology for W-band Amplifier (Invited)" ,URSI AP-RASC 2016, Seoul, Korea, Aug., 2016.

  • T. Kanazawa, T. Amemiya, V. Upadhyaya, A. Ishikawa, K. Tsuruta, T. Tanaka, Y. Miyamoto. "Effect of the HfO2 passivation on HfS2 Transistors", 16th International Conference on Nanotechnology (IEEE NANO 2016), No. ThAM11.3, Aug. 2016.

  • K. Makiyama, S. Ozaki, Y. Niida, T. Ohki, N. Okamoto, Y. Minoura, M. Sato, Y. Kamada, K. Joshin, K. Watanabe and Y. Miyamoto, "InAlGaN/GaN-HEMT device technologies for W-band high-power amplifier (Invited)",2016 Lester Eastman Conference (LEC), pp.31 - 34, http://dx.doi.org/10.1109/LEC.2016.7578927

  • M. Kashiwano, A. Yukimachi and Y. Miyamoto, "Experimental approach for feasibility of superlattice FETs", 2016 Lester Eastman Conference (LEC), pp.8 - 11, http://dx.doi.org/10.1109/LEC.2016.7578921

  • V. Upadhyaya, T. Kanazawa, Y. Miyamoto. "Vacuum annealing and passivation of HfS2 FET for mitigation of atmospheric degradation", 2016 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD2016), A5-7, pp. 231-235, Jul. 2016.

  • Y. Miyamoto, W. Lin, S.Iwata, and K. Fukuda, "Steep sub-threshold slope in short-channel InGaAs TFET (Invited)", The 18th International Symposium on the Physics of Semiconductors and Applications (ISPSA-2016),A6-I-01,Jeju, Korea. July, 2016.

  • W. Lin, S.Iwata, K. Fukuda and Y. Miyamoto, "Scaling limit for InGaAs/GaAsSb heterojunction double-gate tunnel FETs from the viewpoint of direct band-to-band tunneling from source to drain induced off-characteristics deterioration", Jpn. J. Appl. Phys., vol.55, 070303 http://dx.doi.org/10.7567/JJAP.55.070303

  • H. Kinoshita, N. Kise, A. Yukimachi, T. Kanazawa, Y. Miyamoto. "Operation of 16-nm InGaAs channel multi-gate MOSFETs with regrown source/drain", Compound Semiconductor Week (CSW2016), TuD4-2, Jun. 2016.

  • 岩田 真次郎,大橋 一水, 林 文博, 福田 浩一, 宮本 恭幸 "GaAsSb/InGaAsダブルゲートンネルFET におけるソースおよびドレイン不純物濃度依存性", 電気学会論文誌C vol. 136, no.4, pp.467-473, Apr., (2016).

  • 宮本恭幸 “III-V族チャネルを持つMOSFET (特集解説)”, 電気学会論文誌C, vol. 136, no.4, pp.437-443, Apr., (2016).

  • Y. Miyamoto, “Steep slope devices with InGaAs channel for post Si CMOS application (Invited)”, China Semiconductor Technology International Conference (CSTIC) 2016, IX-I-4, Mar, Shanghai, (2016).

  • T. Kanazawa, T. Amemiya, A. Ishikawa, V. Upadhyaya, K. Tsuruta, T. Tanaka, and Y. Miyamoto, "Few-layer HfS2 transistors", Scientific reports, 6, 22277, (2016).

2015年度
  • Y. Miyamoto, “Steep slope devices with InGaAs channel for post Si CMOS application (Invited)”, China Semiconductor Technology International Conference (CSTIC) 2016, IX-I-4, Mar, Shanghai, (2016) .

  • F. A. Fatah, Y.-C. Lin, R.-X. Liu, K.-C. Yang, T.-W. Lin, H.-T. Hsu, J.-H. Yang, Y. Miyamoto, H. Iwai, C. Hu, S. Salahuddin and E. Y. Chang,“A 60-nm-thick enhancement mode In0.65Ga0.35As/InAs/ In0.65Ga0.35As high-electron-mobility transistor fabricated using Au/Pt/Ti non-annealed ohmic technology for low-power logic applications,” Applied Physics Express 9, 026502 (2016)

  • F. A. Fatah, Y.-C. Lin, T.-Y. Lee, K.-C. Yang, R.-X. Liu, J.-R. Chan, H.-T. Hsu, Y. Miyamoto and E. Y. Chang, “Potential of Enhancement Mode In0.65Ga0.35As/InAs/In0.65Ga0.35As HEMTs for Using in High-Speed and Low-Power Logic Applications”. Solid State Sci. Technol. 2015 volume 4, issue 12, N157-N159.

  • K. Makiyama, S. Ozaki, T. Ohki, N. Okamoto, Y. Minoura, Y. Niida, Y. Kamada, K. Joshin, K. Watanabe, Y. Miyamoto,"Collapse Free High Power InAlGaN/GaN-HEMT with 3 W/mm at 96 GHz",2015 IEEE International Electron Devices Meeting (IEDM), 9.1, Dec., Washington DC, (2015)

  • S. Iwata, W. Lin, K. Fukuda and Y. Miyamoto "Design of drain for low off current in GaAsSb/InGaAs tunnel FETs", 2015 International Conference on Solid State Devices and Materials (SSDM), PS-6-25, Sapporo, Japan, Sept. 2015.

  • T. Kanazawa, T. Amemiya, A. Ishikawa, V. Upadhyaya, T. Tanaka, K. Tsuruta, and Y. Miyamoto, "HfS2 Electron Double Layer Transistor with High Drain Current", 2015 International Conference on Solid State Devices and Materials (SSDM), D-2-5, Sapporo, Japan, Sept. 2015

  • Y. Miyamoto,T. Kanazawa, Y. Yonai, K. Ohsawa, Y. Mishima, M. Fujimatsu, K. Ohashi, S. Nestu, and S. Iwata "InGaAs channel for low supply voltage (Invited)", 2015 International Conference on Solid State Devices and Materials (SSDM), Sapporo, Japan, Sept. 2015

  • Y. Miyamoto, M. Fujimatsu, K. Ohashi, A. Yukimachi and S. Iwata, "Steep subthreshold slope in InGaAs MOSFET (Invited)", SemiconNano2015, Hsinchu, Taiwan, Sept. 2015

  • H.Kinoshita,S.Netsu,Y.mishima,T.Kanazawa and Y.Miyamoto, "Fabrication of InGaAs channel multi-gate MOSFETs with MOVPE regrown source/drain", 11th Topical Workshop on Heterostructure Microelectronics (TWHM 2015), Takayama, Japan, 7-6, Aug. 2015.

  • K. Ohsawa, Y. Mishima and Y. Miyamoto, "Operation of 13-nm channel length InGaAs-MOSFET with n-InP source",27th International Conference on Indium Phosphide and Related Materials, E.6.3, July, 2015.

  • S. Netsu, T. Kanazawa, and Y. Miyamoto, 'Improvement of Interface Property of HfO2/Al2O3/In0.53Ga0.47As Using Nitrogen Plasma Cleaning and Hydrogen Annealing', 27th International Conference on Indium Phosphide and Related Materials, E.6.4, July, 2015.

  • T. Kanazawa, T. Amemiya, A. Ishikawa, V. Upadhyaya, K. Tsuruta, T. Tanaka, and Y. Miyamoto, "Fabrication of Thin-Film HfS2 FET", 73rd Device Research Conference (DRC), V-A-5, Columbus, OH, CA, June 2015.

  • R Yamanaka, T. Kanazawa, E. Yagyu and Y. Miyamoto, ,” Normally-off AlGaN/GaN high-electron-mobility transistor using digital etching technique”, Jpn. J. Appl.Phys., 54, 06FG04, June., (2015). doi:10.7567/JJAP.54.06FG04

  • K. Ohashi, M. Fujimatsu, S. Iwata and Y. Miyamoto, "Body width dependence of subthreshold slope and on-current in GaAsSb/InGaAs double-gate vertical tunnel FETs", Jpn. J. Appl.Phys., 54, 04Df10, Apr., (2015). doi:10.7567/JJAP.54.04DF10

2014年度
  • R. Yamanaka, T. Kanazawa, E. Yagyu, and Y. Miyamoto, "Normally-off AlGaN/GaN HEMT using Digital Etching Technique", 2014 International Microprocesses and Nanotechnology Conference (MNC), Fukuoka, Japan, 7P-11-49, Nov., 2014.

  • K. Ohashi, M. Fujimatsu and Y. Miyamoto, "Body width dependence of subthreshold slope and on-current in GaAsSb/InGaAs Double Gate Vertical Tunnel FETs", 2014 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, Sept. 2014.

  • K. Ohsawa, A. Kato, T. Kanazawa, E. Uehara and Y. Miyamoto, “Channel thickness dependence on InGaAs MOSFET with InP source for high current density”, IEICE Electronics Express, vol.11, No. 14, pp.1-5. (2014).

  • Y. Miyamoto, T. Kanazawa, Y. Yonai, K. Ohsawa, Y. Mishima, T. Irisawa, M. Oda, and T. Tezuka, "Growth Process for High Performance of InGaAs MOSFETs (Invited)", 72nd Device Research Conference (DRC), Santa Barbara, CA, III-32, June 2014.

  • Y. Mishima, T. Kanazawa, H. Kinoshita, E. Uehara, and Y. Miyamoto, "InGaAs tri-gate MOSFETs with MOVPE regrown source/drain", 72nd Device Research Conference (DRC), Santa Barbara, CA, III-32, June 2014.

  • T. Amemiya, T. Kanazawa, A. Ishikawa, J. Kang, N. Nishiyama, Y. Miyamoto, T. Tanaka, and S. Arai, “Permeability control in InP-based photonic platforms,” [Invited] The Collaborative Conference on Materials Research (CCMR) 2014, Korea, June 2014

  • Y. Atsumi, N. Taksatorn, N. Nishiyama, Y. Miyamoto and S. Arai, "Loss reduction of Si optical waveguides by beam step-size fracturing technique in electron beam lithography",  Jpn. J. Appl.Phys., 53, 06JB04, June, (2014).

  • Y. Miyamoto, T. Kanazawa, Y. Yonai, A. Kato, M. Fujimatsu, M. Kashiwano , K. Ohsawa, and K. Ohashi, "InGaAs MOSFET Source Structures Toward High Speed/low Power Applications (Invited)", 26th International Conference on InP and Related Materials (IPRM 2014), Montpellier, France, Tu-B1-5, May 2014.

  • M. Yamada, K. Uchida, and Y. Miyamoto, “Delay time component of InGaAs MOSFET caused by dynamic source resistance” IEICE Trans. Electron., Vol. E97-C, No.5, pp.419-422 (2014).

2013年度
  • T. Irisawa, M. Oda, K. Ikeda, Y. Moriyama, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata, Y. Miyamoto and T. Tezuka, “High Electron Mobility Triangular InGaAs-OI nMOSFETs with (111)B Side Surfaces Formed by MOVPE Growth on Narrow Fin Structures,” IEDM2013 Tech. Dig., pp. 28-31, Dec. Washington, DC, Dec 2013. (DOI: 10.1109/IEDM.2013.6724542)

  • Y. Miyamoto, T. Kanazawa, Y. Yonai, A. Kato, K. Ohsawa, M. Oda, T. Irisawa, and T. Tezuka, “Heavily doped epitaxially grown source in InGaAs MOSFET for high drain current density” [Invited], 44th IEEE Semiconductor Interface Specialists Conference (SICS 2013), Arlington, VA, 9.1 6, Dec. 2013.

  • Y. Atsumi, N. Taksatorn, N. Nishiyama, Y. Miyamoto and S. Arai, "Miniaturization of Exposure Area for Electron Beam Lithography using Proximity Effect Correction toward Si Optical Circuits", 2014 International Microprocesses and Nanotechnology Conference (MNC), Sapporo, Japan, 6C-3-4, Nov., 2013.

  • T. Amemiya, T. Kanazawa, A. Ishikawa, S. Myoga, J. Kang, N. Nishiyama, Y. Miyamoto, T. Tanaka, and S. Arai, “ Photonic metamaterials in semiconductor optical devices,” [Invited] 2013 EMN Open Access Week, China, Oct. 2013.

  • M. Oda, T. Irisawa, E. Mieda, Y. Kurashima, H. Takagi, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Ishihara, T. Osada, Y. Miyamoto, T. Tezuka, "Suppression of short channel effects in accumulation-type UTB-InGaAs-OI nMISFETs with raised S/D fabricated by gate-last process," 2013 International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, PS-3-20, Sept. 2013.

  • Y. Yamaguchi, K. Hayashi, T. Oishi, H. Otsuka, K. Yamanaka, and Y. Miyamoto, “Analysis on trade-off between drain resistance and drain-source capacitance of source field plate GaN HEMT,” 2013 International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, J-6-3, Sept. 2013.

  • M. Kashiwano, A. Yukimachi, and Y. Miyamoto, “Dependence of the Carrier Concentration in InGaAs/InP Superlattice-based FETs with a Steep Subthreshold Slope,” 2013 International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, D-7-3, Sept. 2013.

  • K. Ohsawa, A. Kato, T. Sagai, T. Kanazawa, E. Uehara, and Y. Miyamoto, “Channel thickness dependence on InGaAs MOSFET with n-InP source for high current density," 10th Topical Workshop on Heterostructure Microelectronics (TWHM 2013), Hakodate, Japan, 2-9, pp. 19-20, Sept. 2013.

  • 林一夫、大石敏之 、賀茂宣卓、山口裕太郎、大塚浩志、山中宏治、中山正敏、宮本恭幸:「AlGaN/GaN HEMTにおけるドレーン漏れ電流の解析」, 電子情報通信学会論文誌. C エレクトロニクス, Vol. J96-C, No. 8, pp. 200-208, Aug. 2013.

  • 上澤岳史、宮本恭幸:「縦型ゲートホットエレクトロントランジスタの新しい遮断周波数算出方法」, 電子情報通信学会論文誌. C エレクトロニクス, Vol. J96-C, No. 7, pp. 174-179, July 2013.

  • Y. Miyamoto, “InGaAs channel MOSFET for high-speed/low-power application” [Invited], The 16th International Symposium on the Physics of Semiconductors and Applications (ISPSA), Jeju, Korea, A1-I-01, July 2013.

  • T. Amemiya, T. Kanazawa, A. Ishikawa,S. Myoga, E. Murai, T. Shindo, J. Kang, N. Nishiyama, Y. Miyamoto, T. Tanaka, and S. Arai, “Electrically-driven Permeability-controlled Optical Modulator using Mach-Zehnder Interferometer with Metamaterial,” The Conference on Lasers and Electro-Optics 2013 (CLEO 2013), USA, QM1A.6, June 2013.

  • A. Kato, T. Kanazawa, E. Uehara, Y. Yonai, and Y. Miyamoto, “Sub-50-nm InGaAs MOSFET with n-InP source on Si Substrate,” 25th Int. Conf. Indium Phosphide and Related Materials (IPRM2013) , Kobe, Japan, WeD1-2, May 2013.

  • M. Kashiwano, J. Hirai, S. Ikeda, M. Fujimatsu, and Y. Miyamoto, “High Open-Circuit Voltage Gain in Vertical InGaAs Channel Metal-Insulator Semiconductor Field Effect Transistor Using Heavily Doped Drain Region and Narrow Channel Mesa,” Jpn. J. Appl. Phys., Vol. 52, pp. 04CF05-1-4, Apr. 2013. (DOI: 10.7567/JJAP.52.04CF05)

  • K. Hayashi, Y. Yamaguchi, T. Oishi, H. Otsuka, K. Yamanaka, M. Nakayama, and Y. Miyamoto, “Mechanism Study of Gate Leakage Current for AlGaN/GaN High Electron Mobility Transistor Structure Under High Reverse Bias by Thin Surface Barrier Model and Technology Computer Aided Design Simulation,” Jpn. J. Appl. Phys., Vol. 52, pp. 04CF12-1-6, Apr. 2013. (DOI: 10.7567/JJAP.52.04CF12)

2012年度
  • M. Kashiwano, J. Hirai, S. Ikeda, M. Fujimatsu and Y. Miyamoto, "High Open Circuit Voltage Gain in Vertical InGaAs Channel Metal-Insulator-Semiconductor Field-Effect Transistor using Heavily Doped Drain Region and Narrow Channel Mesa", 2012 International Conference on. Solid State Devices and Materials (SSDM 2012), F-3-2, Kyoto, Sept., 2012.

  • T. Oishi, K. Hayashi, Y. Yamaguchi, H. Otsuka, K. Yamanaka, M. Nakayama and Y. Miyamoto, "Mechanism study of gate leakage current for AlGaN/GaN HEMT structure under high reverse bias by TSB model and TCAD simulation", 2012 International Conference on. Solid State Devices and Materials (SSDM 2012), F-7-4, Kyoto, Sept., 2012.

  • Y. Yamaguchi, K. Hayashi, T. Oishi, H. Otsuka, K. Yamanaka, M. Nakayama and Y. Miyamoto,"Analysis on trade-off between electric field and gate-drain capacitance for GaN HEMT by T-CAD simulation", 2012 International Conference on. Solid State Devices and Materials (SSDM 2012), PS-6-21, Kyoto, Sept., 2012.

  • K. Tanaka, and Y. Miyamoto,"InP HBT with 55-nm-wide Emitter and Relationship between Emitter Width and Current Density", 24th Int. Conf. Indium Phosphide and Related Materials (IPRM2012),We-1E.1, Aug., Santa Barbara, CA, (2012)

  • M. Fujimatsu, H. Saito, and Y. Miyamoto,, "71 mV/dec of Sub-Threshold Slope in Vertical Tunnel Field-Effect Transistors with GaAsSb/InGaAs Heterostructure", 24th Int. Conf. Indium Phosphide and Related Materials (IPRM2012),Mo-1D.2, Aug., Santa Barbara, CA, (2012)

  • J. Hirai, T. Kususaki, S. Ikeda,and Y. Miyamoto,"Vertical InGaAs MOSFET with HfO2 gate",2012 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices(AWAD), 73, June29, 2012 Okinawa,

  • N. Takebe, and Y. Miyamoto, “Reduction of base-collector capacitance in InP/InGaAs DHBT with buried SiO2 wires” IEICE Trans. Electron., vol. E95-C, no.5, pp.917-920 (2012) .

  • A. Kato T. Kanazawa, S. Ikeda, Y. Yonai, and Y. Miyamoto, “Reduction of access resistance of InP/InGaAs composite-channel MOSFET with back source electrode” IEICE Trans. Electron., vol. E95-C, no.5, pp.904-919 (2012).

2011年度
  • H. Saito and Y. Miyamoto, “Reduction of Output Conductance in Vertical InGaAs Channel Metal?Insulator?Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region”, Applied Phys. Exp., vol.45 no.2, 024101, (2012).

  • Y. Yonai, T. Kanazawa, S. Ikeda, and Y. Miyamoto,"High Drain Current (>2A/mm) InGaAs channel MOSFET at VD=0.5V with Shrinkage of Channel Length by InP Anisotropic Etching", 2011 IEEE International Electron Devices Meeting (IEDM 2011), 13.3m Washington DC, Dec., 2011.

  • Y. Miyamoto, T. Kanazawa and H. Saito, "High-current-density InP ultrafine devices for high-speed operation",(Invited) The International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz), Tu2A.1, Oct., Houston, 2012.

  • M. Fujimatsu, H. Saito and Y. Miyamoto,”GaAsSb/InGaAs vertical tunnel FET with a 25 nm-wide channel mesa structure", 2011 International Conference on Solid State Devices and Materials (SSDM 2011, A-4-1, Nagoya, Sept., 2011.

  • Y. Yamaguchi, T. Sagai and Y. Miyamoto, "Fabrication of InP/InGaAs SHBT on Si Substrate by Using Transferred Substrate Process", 9th Topical Workshop on Heterostructure Materials (TWHM2011),3-5 , Gifu, Aug. 2011.

  • A. Kato, T. Kanazawa, S. Ikeda, Y. Yonai, Y. Miyanoto "Reduction of Access Resistance of InP/InGaAs Composite-Channel MOSFET with A Back Source Electrode", 2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices(AWAD), 2A.10, June29, 2011 Daejeon, Korea

  • N. Takebe, and Y. Miyamoto, "Reduction of Base-Collector Capacitance in InP/InGaAs DHBT with Buried SiO2 Wires", 2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices(AWAD), 2A.8, June29, 2011 Daejeon, Korea

  • N. Takebe, T. Kobayashi, H. Suzuki, Y. Miyamoto, and K. Furuya, "Fabrication of InP/InGaAs DHBTs with buried SiO2 wires", IEICE Trans. Electron., vol. E94-C, no.5, pp.830-834, (2011) .

  • T. Kanazawa, R. Terao, S. Ikeda, and Y. Miyamoto, "MOVPE-regrown source/drain regions for III-V MOSFETs with high drain current of 1.28 A/mm", 23rd Int. Conf. Indium Phosphide and Related Materials (IPRM2011), Postdeadline paper, May 25, Berlin, Germany, (2011)

  • Y. Matsumoto, H. Saito and Y. Miyamoto, "Reduction of source parasitic capacitance in vertical InGaAs MISFET", 23rd Int. Conf. Indium Phosphide and Related Materials (IPRM2011), Tu-5.1.4, May 24, Berlin, Germany, (2011)

  • R. Terao, T. Kanazawa, S. Ikeda, Y. Yonai, A. Kato, and Y. Miyamoto, "InP/InGaAs Composite MOSFETs with Regrown Source and Al2O3 gate dielectric Exhibiting Maximum Drain Current Exceeding 1.3 mA/μm", Applied Phys. Exp., vol.4, no.5, 054201, (2011).

  • M. Yamada, T. Uesawa, Y. Miyamoto, and K. Furuya, ""Deviation from Proportional Relationship between Emitter Charging Time and Inverse Current of Heterojunction Bipolar Transistors Operating at High Current Density", IEEE Electron Device Lett., vol.32 issue.4, pp.491-493, (2011) .

2010年度
  • H. Saito, Y. Matsumoto, Y. Miyamoto, and K. Furuya, “Vertical InGaAs Channel Metal?Insulator?Semiconductor Field Effect Transistor with High Current Density” Jpn. J. Appl. Phys., vol.50 014102 (2011).

  • Chien-I Kuo, Wee Chin Lim, Heng-Tung Hsu, Chin-Te Wang, Li-Han Hsu, Faiz Aizad, Guo-Wei Hung, Yasuyuki Miyamoto and Edward Yi Chang, "Bonding Temperature Effect on the Performance of Flip Chip Assembled 150nm mHEMT Device on Organic Substrate" 2010 International Conference on Enabling Science and Nanotechnology (ESciNano), OB‐03‐11 ID47 KLCC, Kuala Lumpur MALAYSIA Dec., (2010)

  • Y. Miyamoto, H. Saito, and T. Kanazawa, "Submicron-channel InGaAs MISFET with epitaxially grown source", (Invited) 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), p.1307, 1-4 Nov. 2010, Shanghai.

  • T. Kanazawa, R. Terao, Y. Yamaguchi, S. Ikeda, Y. Yonai, and Y. Miyamoto, "InP/InGaAs MOSFET with back-electrode structure bonded on Si substrate using a BCB adhesive Layer", 2010 International Conference on Solid State Devices and Materials (SSDM 2010), I2-2, Tokyo, Sept., 2010.

  • T. Kanazawa, K. Wakabayashi, H. Saito, R. Terao, S. Ikeda, Y. Miyamoto, and K. Furuya “Submicron InP/InGaAs Composite-Channel Metal?Oxide?Semiconductor Field-Effect Transistor with Selectively Regrown n-Source", Applied Phys. Exp., vol.3, 094201 (2010).

  • H. Saito, Y. Miyamoto, and K. Furuya, "Fabrication of Vertical InGaAs Channel Metal-Insulator-Semiconductor Field Effect Transistor with a 15-nm-wide Mesa Structure and a Drain Current Density of 7 MA/cm2", Applied Phys. Exp., vol.3, 084101 (2010).

  • C-I. Kuo, H-T. Hsu, Y-L. Chen, C-Y. Wu, E. Y. Chang, Y. Miyamoto, W-C. Tsern, and K. C. Sahoo, “RF Performance Improvement of Metamorphic High-Electron Mobility Transistor Using (InxGa1 - xAs)m/(InAs)n Superlattice-Channel Structure for Millimeter-Wave Applications” IEEE Electron Device Letters, vol.32 677-679 July (2010).

  • N. Takebe, T. Kobayashi, H. Suzuki, Y. Miyamoto, and K. Furuya, "Fabrication of InP/InGaAs DHBTs with buried SiO2 wires", 2010 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices(AWAD), 2B.4, June 30 ?July 2nd, 2010 / O-okayama, Tokyo.)

  • Y. Miyamoto, T. Kanazawa, and H. Saito, "InGaAs MISFET with epitaxially grown source (Invited)" The 3rd International Symposium on Organic and Inorganic Electronic Materials and Related Nanotechnologies (EM-NANO 2010) June. 23th, 2010. Toyama, Japan

  • M. Yamada, T. Uesawa, Y. Miyamoto, and K. Furuya, "Deviation from Proportional Relationship between Emitter Charging Time and Inverse Current of Heterojunction Bipolar Transistors Operating at High Current Density", 37th International Symposium on Compound Semiconductor (ISCS’10), TuP1, June, 2010. Takamatsu, Japan

  • T. Kanazawa, K. Wakabayashi, H. Saito, R. Terao, T. Tajima, S. Ikeda, Y. Miyamoto and K. Furuya, "Submicron InP/InGaAs composite channel MOSFETs with selectively regrown n+-source/drain buried in channel undercut", 22nd Int. Conf. Indium Phosphide and Related Materials (IPRM2010), TuB2-3, June, 2010. Takamatsu, Japan

  • H. Saito, Y. Miyamoto, and K. Furuya "Vertical InGaAs FET with hetero-launcher and undoped channel", 22nd Int. Conf. Indium Phosphide and Related Materials (IPRM2010), WeB2-4, June. 2nd, 2010. Takamatsu, Japan.

  • C.-T. Wang, C.-I. Kuo, W.-C. Lim, L.-H. Hsu, H.-T. Hsu, Y. Miyamoto, E.Y. Chang, S.-P. Tsai and Y.-S. Chiu, "An 80 nm In0.7Ga0.3As MHEMT with Flip-Chip Packaging for W-Band Low Noise Applications",22nd Int. Conf. Indium Phosphide and Related Materials (IPRM2010), WeP44, June. 2nd, 2010. Takamatsu, Japan.

  • Faiz Aizad, Heng-Tung Hsu, Chien-I Kuo, Chien-Ying Wu, Edward Yi Chang,Yasuyuki Miyamoto, Guo-Wei Huang, Yu-Lin Chen, and Yu-Sheng Chiu, " Investigation Logic Performances of 80-nm HEMTs for InxGa1−xAs ", 37th International Symposium on Compound Semiconductor (ISCS’10), WeD3-3, June, 2010. Takamatsu, Japan

  • Y. Miyamoto, S. Takahashi, T. Kobayashi, H. Suzuzki, and K. Furuya,"Estimation of collector current spreading in InGaAs SHBT having 75-nm-thick collector", IEICE Trans. Electron., vol. E93-C, No. 5, pp.644-647, May (2010) .

2009年度
  • Chia-Ta Chang, Heng-Tung Hsu, Edward Yi Chang, Chien-I Kuo, Jui-Chien Huang, Chung-Yu Lu, and Yasuyuki Miyamoto, "30-GHz Low-Noise Performance of 100-nm-Gate-Recessed n-GaN/AlGaN/GaN HEMTs", IEEE Electron Device Letters, vol.31 issue.2, pp.105 - 107, (2010)

  • T. Uesawa, M. Yamada, Y. Miyamoto, and K. Furuya, “Monte Carlo Analysis of Base Transit Times of InP/GaInAs Heterojunction Bipolar Transistors with Ultrathin Graded Bases”, Jpn. J. Appl. Phys., 49 (2010) 024302.

  • Y. Miyamoto, "Vertical InGaAs FET with hetero-launcher and undoped channel", International Symposium on Advanced Nanodevices and Nanotechnology (ISANN), Maui, Dec., 2009.

  • Chia-Yuan Chang, Heng-Tung Hsu, Edward Yi Chang, Hai-Dang Trinh, and Yasuyuki Miyamoto, “InAs-Channel Metal-Oxide-Semiconductor HEMTs with Atomic-Layer-Deposited Al2O3 Gate Dielectric”, Electrochemical and Solid-State Letters, vol.12, no.12, H456-H459, 2009.

  • Y. Miyamoto, "InGaAs/InP MISFET (Invited) ", International Symposium on Silicon Nano Devices in 2030, 3-2, Tokyo, Oct., 2009.

  • T. Kanazawa, H. Saito, K. Wakabayashi, T. Tajima, R. Terao, Y. Miyamoto and K. Furuya, "Fabrication of InP/InGaAs Undoped Channel MOSFET with Selectively Regrown N+-InGaAs Source Region", 2009 International Conference on Solid State Devices and Materials (SSDM 2009), J-2-2, Sendai, Oct., 2009.

  • Y. Miyamoto, H. Yashita, N. Takabe, and K. Furuya, "In-situ Etching in MOVPE for Thin Collector of InP HBT with Buried SiO2 Wire", Topical Workshop on Heterostructure Materials (TWHM2009), WeC-7 , Nagano, Aug. 2009.

  • T. Uesawa, M. Yamada, Y. Miyamoto, and K. Furuya, "Monte Carlo Analysis of Base Transit Times of InP/Gaines Heterojunction Bipolar Transistors with Ultrathin Bases", Topical Workshop on Heterostructure Materials (TWHM2009), WeC-8 , Nagano, Aug. 2009.

  • Y. Miyamoto, T. Kanazawa, H. Saito, K. Furuya, "InGaAs/InP MISFET with epitaxially grown source (Invited)", 2009 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices(AWAD), 2A.3, June 24 ? 26, 2009 / Haeundae Grand Hotel, Busan, Korea

  • Y. Miyamoto, S. Takahashi, T. Kobayashi, H. Suzuki, K. Furuya, "Evaluation of collector current spreading of InGaAs SHBT with 75-nm-thick collector", 2009 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices(AWAD), 2A.11, June 24 ? 26, 2009 / Haeundae Grand Hotel, Busan, Korea

  • C.-I. Kuo, H.-T. Hsu, Chung Li, C.-Y. Wu, E. Y. Chang, Y. Miyamoto, Y.-L. Chen, and D. Biswas, A 40-nm-Gate InAs/InGaAs Composite-Channel HEMT with 2200 mS/mm and 500-GHz fT, IEEE 21th Conference on Indium Phosphide and Related Materials (IPRM'09), TuA2.4 May 2009, Newport Beach, California

  • H. Saito, Y. Miyamoto, and K. Furuya Vertical InGaAs MOSFET with Hetero-Launcher and Undoped Channel IEEE 21th Conference on Indium Phosphide and Related Materials (IPRM'09) WP16, May 2009, Newport Beach, California

  • T. Kanazawa, H. Saito, K. Wakabayashi, T. Tajima, Y. Miyamoto and K. Furuya,, “InP/InGaAs-channel MOSFET with MOVPE Selective Regrown Source, IEEE 21th Conference on Indium Phosphide and Related Materials (IPRM'09) WP17, May 2009, Newport Beach, California

  • Chia-Yuan Chang, Heng-Tung Hsu, Edward Yi Chang, and Yasuyuki Miyamoto “InAs-Channel High-Electron-Mobility Transistors for Ultralow-Power Low Noise Amplifier Applications”, Japanese Journal of Applied Physics 48 (2009) 04C094

2008年度
  • Y. Miyamoto InGaAs MISFET with hetero-laucher (Invited) 2009 RCIQE International Seminar on "Advanced Semiconductor Materials and Devices" March 2009, Sapporo.

  • Hisashi Saito, Yasuyuki Miyamoto, and Kazuhito Furuya, "Improvement in Gate Insulation in InP Hot Electron Transistors for High Transconductance and High Voltage Gain", Applied Physics Express, 2, 034501 (2009)

  • So Nishimura, Kazuhito Furuya, Yasuyuki Miyamoto “Design and Simulation of Hot-Electron Diffraction Oservation by Scanning Probe ? Quantitative Evaluation of Observation Possibility ?”Jap. J. Appl. Phys. Vol. 47, No. 11, Nov., 2008, pp. 8652-8658.

  • Chien-I KUO, Heng-Tung HSU , Edward Yi CHANG, Yasuyuki MIYAMOTO , and Wen-Chung TSERN,“InAs High Electron Mobility Transistors with Buried Gate for Ultralow-Power-Consumption Low-Noise Ampli?er Application” Jap. J. Appl. Phys. Vol. 47, No. 9, Sept., 2008, pp. 7119?7121

  • Yasuyuki Miyamoto, Takashi Hasegawa, Hisashi Saito, and Kazuhito Furuya, "RF Characteristics of Schottky-Gate-Controlled Hot Electron Transistor", IEEE Nanotechnology Materials and Devices Conference 2008, We P17, Kyoto, Oct., 2008.

  • T. Kanazawa, H. Saito, K. Wakabayashi, Y. Miyamoto and K. Furuya, "Lateral Buried Growth of N+-InGaAs Source/Drain Region to Undercut InGaAs Channel Structure for High Drive Current N-type MOSFET" 2008 International Conference on Solid State Devices and Materials (SSDM 2008), G-2-5, Tsukuba, Sept., 2008.

  • C. Y. Chang, H. T. Hsu, E. Y. Chang, C. I. Kuo and Y. Miyamoto, "InAs-Channel HEMTs for Ultra-Low-Power LNA Applications", 2008 International Conference on Solid State Devices and Materials (SSDM 2008), G-2-3, Tsukuba, Sept., 2008.

  • Hisashi Saito, Takahiro Hino, Yasuyuki Miyamoto, Kazuhito Furuya, "Hot electron transistor controlled by insulated gate with 70nm-wide emitter", EEE 20th Conference on Indium Phosphide and Related Materials (IPRM’08), WeP72, Versailles - France, May, 2008

  • Chien-I Kuo, Edward Yi Chang, Chia-Yuan Chang, Heng-Tung Hsu, Yasuyuki Miyamoto, "Investigation of impact ionization from InXGa1-XAs to InAs channel HEMTs for high speed and low power applications", IEEE 20th Conference on Indium Phosphide and Related Materials (IPRM’08), WeP68, Versailles - France, May, 2008

  • Chien-I Kuo, Heng-Tung Hsu, Edward Yi Chang, Chia-Yuan Chang, Yasuyuki Miyamoto, Suman Datta, Marko Radosavljevic, Guo-Wei Huang, and Ching Ting Lee “RF and Logic Performance Improvement of In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel HEMTs Using Gate-Sinking Technology” IEEE Electron Device Lett., vol.29, No. 4, Apr., 2008.

  • Chien-I Kuo, Heng-Tung Hsu, Edward Yi Chang, Chia-Yuan Chang, Yasuyuki Miyamoto, Suman Datta, Marko Radosavljevic, Guo-Wei Huang, and Ching Ting Lee “RF and Logic Performance Improvement of In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel HEMTs Using Gate-Sinking Technology” IEEE Electron Device Lett., vol.29, No. 4, Apr., 2008.

2007年度
  • Chia-Yuan Chang, Heng-Tung Hsu, E. Y. Chang, Chien-I Kuo, S. Datta, M. Radosavljevic, Y. Miyamoto, and Guo-Wei Huang “Investigation of Impact Ionization in InAs-Channel HEMT for High-Speed and Low-Power Applications”, IEEE Electron Dev. Lett., vol.28, no.10, pp.856-858, 2007.

  • S. Takahashi、T. Miura, H. Yamashita,Y. Miyamoto and K. Furuya,“DC Characterristics of Heterojunction Bipolar Tranistor with Buried SiO2 Wire in Collector,Int Symp.Compound Semiconductors, TuD-P2,Kyoto,Oct,2007

  • H.Yamashita, T.Miura, S.Takahashi, Y.Miyamoto and K.Furuya "Fabrication of 200-nm-thick SiO2 wires buried in InP for reduction in collector capacitance in InP/InGaAs DHBT" Topical Workshop on Heterostructure Materials (TWHM2007), FrC-3 , Kisarazu/Japan, Aug. 2007.

  • K. Nishihori and Y. Miyamoto, “Numerical Analysis of the Effect of P-Regions on the I-V Kink in GaAs MESFETs”, Trans. IECE of Japan, vol.E90-C, no.8, pp.1643-1649, (2007).

  • M. Igarashi, N. Machida, Y. Miyamoto, and K. Furuya, “Cutoff Frequency Characteristics of Insulated-gate Hot-electron Transistors”, 15th International Conference on Nonequilibrium Carrier Dynamics in Semiconductors, (HCIS-15), MoP-45, Tokyo, July, 2007.

  • A. Suwa, T. Hasegawa, T. Hino, H. Saito, M. Oono, Y. Miyamoto, and K. Furuya, "InP/InGaAs hot electron transistors with insulated gate", Jpn. J. Appl. Phys., vol.46, no.25, pp. L617-L619, (2007)

  • Chia-Yuan Chang, Edward Yi Chang, Yi-Chung Lien, Yasuyuki Miyamoto, Chien-I Kuo, Sze-Hung Chang and Li-Hsin Chu, "High-PerformanceIn0.52Al0.48As/In0.6Ga0.4As Power Metamorphic High Electron Mobility Transistor for Ka-Band Applications", Jpn. J. Appl. Phys., vol.46, no.6A, pp. 3385-3387, (2007)

  • T. Hino, A. Suwa, T. Hasegawa, H. Saito, M. Oono, Y. Miyamoto, K. Furuya, "Fabrication of hot electron transistors controlled by insulated gate", 19th International Conference on Indium Phosphide and Related Materials (IPRM'07), PA-11 Matsue, May. 2007

  • N. Kashio, K. Kurishima, Y. Fukai, S. Yamahata, and Y. Miyamoto, メEmitter layer design for highly reliable and high-speed InP HBTsモ, 19th International Conference on Indium Phosphide and Related Materials (IPRM'07) PD1, Matsue, May, 2007.

2006年度
  • A. Suwa, I. Kashima, Y. Miyamoto, and K. Furuya, “Increase of collector current in hot electron transistors controlled by gate bias”, Jpn. J. Appl. Phys., vol.46, no.9, pp.L202-204, (2007) [ABSTRACT & PDF ]

  • Y. Miyamoto, M. Ishida, T. Yamamoto, T. Miura, and K. Furuya, メInP buried growth of SiO2 wires toward reduction of collector capacitance in HBTモ, J. Cryst, Growth, 298, 867-870 (2007).

  • Chia-Yuan Chang, Edward Yi Chang, Yi-Chung Lien, Yasuyuki Miyamoto, Szu-Hung Chen, and Li-Hsin Chu, "High-Performance In0.52Al0.48As/In0.6Ga0.4As Power Metamorphic HEMT for Ka-Band Applications", 2006 IEEE International Conference on Semiconductor Electronics (ICSE2006), Kuala Lumpur, Malaysia, Nov., 2006.

  • T. Kai, Y. Fukuyama, Y. Miyamoto, K. Furuya, K. Kurishima and S. Yamahata, "Electron Beam Lithography for Non Self-Aligned HBTs with Extremely Narrow Emitter Mesa", 2006 International Microprocesses and Nanotechnology Conference, kanagawa, Kamakura, Oct 2006.

  • Y. Miyamoto, R. Nakagawa, I. Kashima, A. Suwa, N. Machida, and K. Furuya, "25-nm-wide emitter for InP hot electron transistors without base layer (Invited)", International Topical Workshop "Tera- and Nano-Devices:Physics and Modeling" III.2, Aizu-Wakamatsu, Oct., 2006.

  • K Furuya, N Machida, M Igarashi, R Nakagawa, I Kashima, M Ishida and Y Miyamoto, "MC simulation of ultrafast transistor using ballistic electron in intrinsic semiconductor and its fabrication feasibility", J. Physics: Conference Series, 38, 208-211,(2006)

  • Nobuya Machida,Yasuyuki Miyamoto,Kazuhito Furuya, "Charging Time of Double-Layer Emitter in Heterojunction Bipolar Transistor Based on Transmission Formalism", Jpn. J. Appl. Phys. Vol.45 (2006) No.35 pp.L935 - L937 [ABSTRACT & PDF ]

  • Yasuyuki MIYAMOTO Ryo NAKAGAWA Issei KASHIMA Masashi ISHIDA Nobuya MACHIDA Kazuhito FURUYA "Current Gain and Voltage Gain in Hot Electron Transistors without Base Layer", Trans. IECE of Japan, vol.E89-C, No.7, .pp.972-978, JULY. 2006

  • Y. Miyamoto, I. Kashima, A. Suwa, and K. Furuya, "Increase in current density at 25-nm-wide emitter for InP hot-electron transistors without base layer", Device Research Conf. V.A-7, University Park, PA, June, 2006.

  • Y. Miyamoto, M.Ishida, T.Yamamoto, T.Miura, and K.Furuya, " InP Buried growth of SiO2 wires toward reduction of collector capacitance in HBT", International Conference on Metalotganic Vapor Phase Epitaxy, (ICMOVPE), Miyazaki, Japan, May, 2005.

  • N. Machida, Y. Miyamoto and K. Furuya, "Minimum Emitter Charging Time for Heterojunction Bipolar Transistors,", International Conference on Indium Phosphide and Related ,WP16 , Pronceton, NJ, May 2005.

2005年度
  • K. Furuya, N. Machida, R. Nakagawa, I. Kashima, M. Ishida, and Y. Miyamoto, メMC simulation and fabrication of ultrafast transistor using ballistic electron in intrinsic semiconductorモ, Second Joint International Conference on New Phenomena in Mesoscopic Systems and Surfaces and Interfaces of Mesoscopic Devices, P28, Maui, USA, Nov. 2005.

  • Y. Miyamoto, R. Nakagawa, I. Kashima, M. Ishida and K. Furuya, "Low leakage gate current of InP transistors with hot electron extracted by attractive potential around i-InP/metal gate", 2005 International Conference on Solid State Devices and Materials (SSDM 2005), I-2-6, Kobe, September, 2005 Kobe,

  • Y Miyamoto, R. Nakagawa, I. Kashima, K. Takeuchi, Y. Yamada, T. Fujisaki, M. Ishida, and K. Furuya, "25 nm Wide Emitter and Precise Alignment between Gate and Emitter in InP Hot Electron Transistors", The 6th Topical Workshop on Heterostructure Microelectronics (TWHM 2005), TuC-3, Awaji-shima. August, 2005.

  • Y. Miyamoto, M. Ishida, T. Nonaka, T. Yamamoto, and K. Furuya,
    "Tungsten Buried Growth by Using Thin Flow-Liner for Small Collector Capacitance in InP HBT",
    International Conference on Indium Phosphide and Related ,TuA-1-4 , Glasgow, May 2005.

  • Y. Miyamoto, Y. Watanabe, W. Qiu, and K. Furaya,
    "Analysis of lateral current spreading in collector of submicron HBT ",
    International Conference on Indium Phosphide and Related ,WP-15 , Glasgow, May 2005.

  • Kazuhito Furuya, Yasunori Ninomiya, Nobuya Machida and Yasuyuki Miyamoto,
    "Double-Slit Interference Observation of Hot Electrons in Semiconductors -- Analysis of Experimental Data --"
    Jpn. J. Appl. Phys. Vol. 44 Part 1, no.5A, 2936-2944 (2005) [ABSTRACT & PDF ]

2004年度
  • Y. Miyamoto, Y. Shirai, M. Yoshizawa and K. Furuya,
    "20 nm Periodical Pattern by Calixarene Resists: Comparison of CMC[4]AOMe with MC[6]AOAc",
    2004 International Microprocesses and Nanotechnology Conference, 28P-6-54, Osaka, Oct., 2004

  • K. Goto,T. Kirigaya,Y. Masuda,Y.-J. Kim,Y. Miyamoto,S. Arai ,
    "Design and Experiments of a Near-Field Optical Disk Head for Very High Efficiency",
    The Journal of Scanning Microscopies, vol.26, no.5, I-68-I-72, (2004)

  • Masaki Yoshizawa, Yasuyuki Miyamoto, Hiroyuki Nakano, Tetsuya Kitagawa, and Shigeru Moriya,
    "Challenges to ultra-thin resist process for LEEPL",
    J. Photopolymer Sci. Technol. 17, 581 (2004).

  • Masaki Yoshizawa, Shigeru Moriya, Hiroyuki Nakano, Yuichi Shirai, Tatsuo Morita, Tetsuya Kitagawa and Yasuyuki Miyamoto,
    " Impact of Latent Image Quality on Line Edge Roughness in Electron Beam Lithography",
    Jpn. J. Appl. Phys. Vol. 43 Part 1, no.6B, 3739-3743 (2004) [ABSTRACT & PDF ]

  • R.Nakagawa, K.Takeuchi, Y.Yamada, Y.Miyamoto and K.Furuya,
    "InP Hot Electron Transistors with Reduced Emitter Width for Controllability of Collector Current by Gate Bias",
    International Conference on Indium Phosphide and Related Materials,P1-14, Kagoshuma, June 2004.

2003年度
  • Kazuki Sasao, Yasuo Azuma, Naotaka Kaneda, Eiji Hase, Yasuyuki Miyamoto and Yutaka Majima,
    "Observation of Current Modulation through Self-Assembled Monolayer Molecule in Transistor Structure",
    Jpn. J. Appl. Phys. Vol. 43 Part 2, no.3A, L337-L339 (2004) [ABSTRACT & PDF ]

  • Katsuhiko Takeuchi, Hiroshi Maeda, Ryo Nakagawa, Yasuyuki Miyamoto and Kazuhito Furuya,
    "InP Hot Electron Transistors with Emitter Mesa Fabricated between Gate Electrodes for Reduction in Emitter-Gate Gate-Leakage Current",
    Jpn. J. Appl. Phys. Vol. 43 Part 2, no.2A, L183-L186 (2004) [ABSTRACT & PDF ]

  • Keigo Yokoyama, Koji Matuda, Toshihiro Nonaka, Yasuyuki Miyamoto, and Kazuhito Furuya,
    "Fabrication of GaInAs/InP heterojunction bipolar transistors with a single tungsten wire as collector electrode",
    Jpn. J. Appl. Phys. Vol. 42 part 2, no.12B, pp. L1501-L1503 (2003) [ABSTRACT & PDF ]

  • Yasuyuki Miyamoto, Ren Yamamoto, Hiroshi Maeda, Katsuhiko Takeuchi, Nobuya Machida, Lars-Erik Wernersson and Kazuhito Furuya,
    "InP Hot Electron Transistors with a Buried Metal Gate",
    Jpn. J. Appl. Phys., vol. 42 part 1, no.12, pp.7221-7226 (2003) [ABSTRACT & PDF ]

  • K. Furuya , Y. Ninomiya , and Y. Miyamoto,
    "Young's Double-Slit Interference Experiment of Hot Electron in Semiconductors",
    Sixth International Conference on New Phenomena in Mesoscopic Systems & Fourth International Conference on Surfaces and Interfaces of Mesoscopic Devices, 1.6,Maui, Dec., 2003

  • Kazuhito Furuya, Yasunori Ninomiya, Nobuya Machida, and Yasuyuki Miyamoto,
    "Young’s Double-Slit Interference Observation of Hot Electrons in Semiconductors"
    Phys. Rev. Lett. 91, 216803, Nov., (2003) [ABSTRACT & PDF ]

  • M. Yoshizawa, S. Moriya, H. Nakano, T. Morita,T. Kitagawa and Y. Miyamoto,
    "The Impact of Latent Image Quality on Line Edge Roughness in Electron Beam Lithography",
    2003 International Microprocesses and Nanotechnology Conference, 30p-6-15

  • K. Sasao, Y. Azuma, N. Kaneda, E. Hase, Y. Miyamoto and Y. Majima
    "Observation of current modulation in SAM-FET fabricated by an air-bridge structure"
    The 2003 International Conference on Solid State Devices and Materials, P7-5, Tokyo, Sept., 2003

  • K. Takeuchi, H. Maeda, R. Makagawa, Y. Miyamoto, and K. Furuya
    "InP hot electron transistors using modulation of gate electrodes"
    The 2003 International Conference on Solid State Devices and Materials, E-7-3, Tokyo, Sept., 2003

  • Tsuyoshi Tanaka, Kohichi Tokudome and Yasuyuki Miyamoto ,
    "Effects of Low-Oxygen-Content Metalorganic Precursors on AlInAs and High Electron Mobility Transistor Structures with the Thick AlInAs Buffer Layer"
    Jpn. J. Appl. Phys. Vol. 42 Part 2, No. 8B, L993-L995 : (2003) [ABSTRACT & PDF ]

  • K. Furuya , Y. Ninomiya , and Y. Miyamoto
    "Young's Double-Slit Interference Experiment of Hot Electron in Semiconductors"
    The 13th International Conference on Nonequilibrium Carrier Dynamics in Semiconductors, Th11.17, July,Modena, 2003

  • Y. Miyamoto and Y. Tohmori
    "Activities of Indium Phosphide in Japan"
    (Invited) GaAs Mantech, 11-1, Scottdale, USA, May 2003

  • T. Tanaka, K. Tokudome, and Y. Miyanmoto,
    "Growth of AlInAs using low-oxygen-content metalorganic precursors and application to HEMT strutures",
    International Conference on Indium Phosphide and Related Materials,ThB 2.4, Santa Barbara, USA, May 2003.

2002年度以前の研究成果